ASIC Digital Designer

The early-career engineer designs and verifies digital architecture for CERN's next-generation radiation-monitoring ASIC, taking RTL through open-source physical-design flows and supporting tapeout, hardware bring-up and integration with analogue and SoC teams.

Department: Health, Safety and Environment — Technology and Systems, Instrumentation and Monitoring Systems

• Design and simulate the ASIC digital architecture
• Verify RTL for safety-critical radiation monitoring
• Prepare floorplans and physical designs for tapeout
• Support post-fabrication bring-up and characterization
• Debug functional and performance issues in hardware
• Coordinate analogue, verification and SoC integration

• Bachelor's or master's degree focused on electronics
• No more than two years of professional experience since graduation
• No PhD and no previous CERN fellow or graduate contract
• Nationality of a CERN Member State or Associate Member State
• Experience using open-source ASIC EDA flows from RTL to GDSII
• English proficiency

• Hybrid CERN graduate role; applicants must have no more than two years of post-graduation experience and cannot hold a PhD